In recent years, it has become very difficult to diagnose failures in, and to measure the performance of, state-of-the-art microprocessors. This is because modern microprocessors not only run at very high clock speeds, but may also execute instructions in parallel, out of program order, and speculatively. Moreover, visibility of a microprocessor's inner state has become increasingly limited due to 1) the complexity of microprocessors (i.e., greater functionality), and 2) practical constraints on the number of externally available contact pads that can be provided on a chip package.
In the past, traditional failure diagnosis and performance measurement tools have been external logic analyzers and in-circuit emulators. Logic analyzers are capable of 1) monitoring signals on external contact pads and/or signals which are otherwise externally accessible, 2) capturing the state of these signals, and 3) generating triggers in response to the captured signal states. However, since logic analyzers rely solely on externally available signals, they cannot analyze and/or trigger on signals which are entirely internal to a chip (i.e., signals that do not make it to the "top", or surface, of a chip). In-circuit emulators, on the other hand, may be used to mimic the functionality of a microprocessor and add visibility to the microprocessor's internal state and signals--but again there are disadvantages to such a tool. Since an in-circuit emulator only emulates a microprocessor's functionality, it cannot give an entirely accurate representation of how a silicon embodiment of a microprocessor will perform. As a result, emulators are more useful for debugging system software than system hardware (such as a microprocessor).
A need therefore exists for a comprehensive system and method for enabling microprocessor and system designers to debug state-of-the-art microprocessors and systems more easily. More specifically, there exists a need for an on-chip system and method of generating and handling a hardware breakpoint trap (HBT). The system and method should be capable of generating a HBT in response to internal signal triggers, should have a great degree of programming flexibility, and should be capable of handling a HBT in a manner that is non-destructive to a microprocessor's current architected state.
It is therefore a primary object of this invention to provide a system and method which enables the debug of a microprocessor, wherein the system and method are implemented internally to a silicon embodiment of a microprocessor.
Another primary object of this invention is to provide an on-chip debug system and method which allows a user to program a variety of on-chip hardware triggers, which when programmed, allow a user to generate a HBT in response to complex matches of signal triggers and other on-chip conditions.
A further object of this invention is to provide a system and method of handling a HBT wherein a microprocessor's architected state is preserved prior to handling the HBT, and restored prior to returning from the HBT. A HBT is therefore handled in a non-destructive manner.
Yet another object of this invention is to provide a system and method of generating and handling a HBT which provides for a great amount of debug flexibility and functionality, yet does so with a simple and cost effective implementation.
A system and method which fulfills the above objects will provide greater visibility of a chip's internal state, yet not interfere with the normal operation of a silicon device (i.e., test and debug will occur under actual system environment conditions, and while a microprocessor is running "at speed").